Track-and-hold circuits are used in many electronic devices. A track-and-hold circuit operates in response to a control signal. In one state of the control signal, the output of the track-and-hold circuit follows the input of the track-and-hold circuit. In the other state of the control signal, the output is held at a constant level equal to the level of the input when the state of the control signal changed.
In one exemplary application of track-and-hold circuits described by Neff in U.S. Pat. No. 6,259,281, assigned to the assignee of this disclosure and incorporated by reference, a high-speed analog-to-digital converter incorporates multiple track-and-hold circuits. The output of each track-and-hold circuit is connected to the analog input of a respective analog-to-digital converter circuit. The inputs of the track-and-hold circuits are all connected to receive the analog input signal. The track-and-hold circuits are each controlled by a respective phase of a multi-phase control signal. The number of phases of the control signal is equal to the number of track-and-hold circuits. The output of each track-and-hold circuit follows the analog input signal and then is held at a constant level as described above. The time at which each track-and-hold circuit switches to its HOLD state is determined by the phase of the control signal received by the track-and-hold circuit. Each track-and-hold circuit holds its output at a constant level long enough for the corresponding analog-to-digital converter circuit to convert the output level to a respective digital value. With this arrangement, the analog-to-digital converter has a maximum sampling rate that is a multiple of the maximum sampling rate of its constituent analog-to-digital converter circuits, where the multiple is equal to the number of analog-to-digital converter circuits.
Track-and-hold circuits have traditionally been voltage-mode devices that track a voltage input and provide a voltage output. More recently, as track-and-hold circuits have been made using higher-speed fabrication processes that require a substantially reduced supply voltage, the use of current-mode track-and-hold circuits that track a current input and generate a current output has increased. However, even current-mode track-and-hold circuits are subject to voltage swing limitations.
FIG. 1 is a schematic circuit diagram of a conventional current-mode track-and-hold circuit 10 in accordance with the prior art. The track-and-hold circuit is structured as a cascode current mirror circuit with a switch connected between the gates of the lower transistors. Specifically, track-and-hold circuit 10 is composed of a cascode input stage 20, a cascode output stage 22 and a switch 26.
Cascode input stage 20 is composed of an input transistor 30 and a first cascode transistor 32. Input transistor 30 has its source connected to supply rail VSS, its gate connected to the drain of first cascode transistor 32 and to switch 26, and its drain connected to the source of first cascode transistor 32. First cascode transistor 32 has its drain connected to an input terminal 34 from which it receives an input current IIN and its gate connected to a static bias voltage supply VB.
Cascode output stage 22 is composed of an output transistor 40 and a second cascode transistor 42. Output transistor 40 has its source connected to supply rail VSS, its gate connected to switch 26, and its drain connected to the source of second cascode transistor 42. Second cascode transistor 42 has its gate connected to static bias voltage supply VB and its drain connected to output terminal 44 to which it provides an output current IOUT. Embodiments for use in high-resolution, low-speed applications may additionally have a hold capacitor (not shown) connected between gate and source of output transistor 40.
To simplify the drawings, the source, gate and drain of the transistors that form the various track-and-hold circuits described in this disclosure are not identified by individual reference numerals. FIG. 2 is a schematic diagram of an exemplary transistor 60 in which the source, gate and drain are identified by the reference numerals 62, 64 and 66 respectively.
In a TRACK mode of track-and-hold circuit 10, switch 26 is closed and the output current IOUT and the input current IIN have a ratio defined by the ratio m of the width-to-length ratio of the channel of output transistor 40 to that of input transistor 30. Since transistors, such as output transistor 40 and input transistor 30, that provide a defined ratio between currents typically have equal channel lengths, the ratio m is typically defined by the ratio of the width of the channel of output transistor 40 to the width of the channel of input transistor 30.
Switch 26 opens to switch track-and-hold circuit 10 to a HOLD mode. In the HOLD mode, switch 26 is open and the voltage formerly applied through switch 26 to the gate of output transistor 40 continues to be applied by the parasitic capacitance of the gate of output transistor 40. The voltage held by the parasitic capacitance maintains the output current IOUT at a fixed level equal to its level at the time switch 26 opened. The output current remains at this level until switch 26 closes once again to restore track-and-hold circuit 10 to the TRACK state.
For proper operation of track-and-hold circuit 10, all four transistors 30, 32, 40 and 42 (collectively, the transistors) are kept in saturation. An analysis of the conditions for saturation shows that the maximum peak-to-peak voltage swing allowed on input terminal 34 of track-and-hold circuit 10 is approximately Vt−Vov where Vt is the threshold voltage of the transistors and Vov is the gate overdrive voltage of first cascode transistor 32. The gate overdrive voltage is the difference between the gate-source voltage and the threshold voltage (Vgs−Vt) of first cascode transistor 32. In other words, the maximum peak-to-peak voltage swing allowed on input terminal 34 is less than the threshold voltage of the transistors.
The maximum peak-to-peak voltage swing allowed at the input terminal 34 of track-and-hold circuit 10 limits the achievable signal-to-noise ratio (SNR) of track-and-hold circuit 10. The SNR is determined by the ratio of the RMS signal voltage at the gate of output transistor 40 to the RMS thermal noise voltage at the gate of output transistor 40. The RMS thermal noise voltage is approximately √(kT/Ch), where k is Boltzmann's constant, T is the absolute temperature and Ch is the hold capacitance, i.e., the capacitance at the gate of output transistor 40. The principal component of the hold capacitance Ch is the gate-to-source capacitance of output transistor 40. The hold capacitance additionally comprises wiring capacitance and the parasitic capacitance of switch 26.
With a sinusoidal input signal, the maximum RMS input voltage allowed at the gate of output transistor 40 is approximately Vt/√8. Consequently, the maximum 3SNR is approximately Vt√(Ch/8kT).
Increasing the SNR of conventional track-and-hold circuit 10 is difficult. The threshold voltage Vt is determined by the IC process used to fabricate the track-and-hold circuit. It is typically expensive and inconvenient to improve the SNR by applying cooling to reduce the temperature of the circuit. The remaining variable that can be changed to increase the SNR is the hold capacitance Ch. However, increasing the hold capacitance Ch results in a proportional increase in the power consumption of track-and-hold circuit 10. Moreover, power consumption increases in direct proportion to the increase in the hold capacitance whereas the SNR only improves by the square root of the increase in the hold capacitance. This means, for example, that achieving a 3 dB improvement in SNR, i.e., doubling the SNR, multiplies the power consumption by a factor of four. With the current trend towards reducing power consumption, multiplying the power consumption is undesirable.
Accordingly, what is needed is a way to increase the SNR of a track-and-hold circuit without multiplying the power consumption and without other undesirable side effects.